As background for our invention, U.S. Pat. No. 4,617,529, issued Oct. 14, 1986, to A. Suzuki shows a ring oscillator composed of CMOS inverters coupled in cascade with a RC delay element inserted between adjacent inverters. However, this prior art uses a fixed delay element and has no other means of variability, making it unusable as a voltage controlled oscillator.
In addition, we would note that there are patents of which we are aware which are listed below with a brief discussion of each of the patents.
U.S. Pat. No. 4,859,970, issued Aug. 22, 1989 to Matsuo et al. and assigned to Kabushiki Kaisha Toshiba, shows a Voltage Controlled Oscillator, one element of which is a voltage controlled delay element comprising CMOS transmission gates connected between adjacent CMOS inverters. The gate of each of the PMOS and NMOS transistors of each transmission gate is connected to a variable control voltage which is used to vary the delay. This circuit does not have a MOS capacitor on the output of the transmission gate structure but uses the parasitic capacitance of the devices and the inverter gates to form the capacitance of the RC delay element needed. This circuit is not an oscillator but requires a phase comparator and other elements of a phase locked loop to generate a stable oscillation.
U.S. Pat. No. 4,517,532, issued May 14, 1985 to R. A. Neidorff and assigned to Motorola, Inc shows a ring oscillator composed of a plurality of inverting gates connected in a loop configuration which has a bypass mechanism which is used to alter the frequency of oscillation. This circuit may be varied in discrete steps only and has no voltage control nor continuous variability. Its preferred embodiment is bipolar 12L and not CMOS.
U.S. Pat. No. 4,884,041, issued Nov. 28, 1989 to R. C. Walker and assigned to the Hewlett-Packard Company, shows a ring oscillator which may be integrated on chip comprising an N element ring oscillator merged with an M element ring oscillator by using a linear combining circuit. Variation of the control voltage allows variation of the oscillator frequency by varying the proportion of combination of the M and N stage oscillator outputs, not by varying the frequency of the individual oscillators using a voltage controlled delay. The control voltage in the patent must take on only a small number of discrete values due to the inherent nature of the combining circuit.
U.S. Pat. No. 4,105,950, issued Aug. 8, 1978 to A. G. F. Dingwall and assigned to the RCA Corporation, shows a VCO comprised of nested oscillating loops one element of which is a CMOS inverter wherein a control voltage is coupled to cause the frequency of oscillation to change in response to changes in the control voltage. However, the control voltage causes a variation in the source voltage of the PMOS transistor of the inverter and a variation in the drain voltage of the NMOS transistor of the inverter, and is not a transmission gate. This causes the voltage swing of the output to be less than the full Vdd to Vss possible with a normal inverter and severely limits the frequency variation possible by varying the control voltage.
U.S. Pat. No. 4,458,165, issued Jul. 3, 1984 to R. M. Jackson and assigned to Tektronix, Inc. shows a delay element composed of cascaded inverters which can be programmed to different delays by bypassing inverter stages using standard digital multiplexor logic. There is no continuous variability and all preferred embodiments require edge triggered flip-flops which are difficult to build and consume large circuit area in the CMOS technology.
U.S. Pat. No. 4,388,537, issued Jun. 14, 1983 to A. Kanuma and assigned to Tokyo Shibaura Denki Kabushiki Kaisha discloses a substrate bias generator which includes a voltage controlled oscillator whose oscillation frequency is controlled in accordance with a feedback voltage derived from the substrate bias voltage. This circuit is composed of NMOS inverters connected in a loop. Each inverter is connected to the following inverter in cascade through an NMOS transmission gate with a MOS capacitor inserted at the output of the transmission gate. It does not use CMOS inverter or transmission gate circuits and thus consumes DC power. The voltage control of the oscillator frequency is an AC voltage derived from the oscillator output and is not a DC control voltage.
Japanese Patent Literature (J03192812) shows a ring oscillator composed of NMOS inverters in cascade connected in a loop with each inverter connected to the following inverter in cascade through an NMOS transmission gate. The gate of the NMOS transmission gate is connected to a DC control voltage which varies the DC resistance of the transmission gate to vary the frequency of oscillation. This circuit does not use CMOS nor a fixed capacitor thus increasing the power consumed and limiting the range of variation of frequency.
U.S. Pat. No. 4,547,749, issued Oct. 15, 1985 to C. C. K. Kuo and assigned to Motorola, Inc. shows a voltage and temperature compensated FET ring oscillator composed of 3 NMOS inverters connected in a loop with the output of each inverter connected to the input of the next inverter in cascade through an NMOS transmission gate. The output of the transmission gate is connected to an NMOS capacitor whose other side is connected to the reference voltage terminal. The gate terminals of the transmission gate devices are driven by a voltage derived from the supply voltage which varies with temperature. It therefore is a DC control voltage which varies the frequency of oscillation to compensate for circuit temperature variations. The circuit is connected between a voltage compensated node and ground and as such does not have a full voltage swing between Vdd and ground. This prevents its use for driving logic without special voltage translation circuits. It also consumes DC power since it does not use CMOS gates.